Integrated circuit memories that are used for electronic data storage include dynamic random access memories (DRAMs), static random access memories (SRAMs), electrically erasable and programmable read only memories (EEPROMs), synchronous random access memories or other types of memories that include a matrix of selectively addressable memory cells.
For example, FIG. 1 is a floorplan block diagram that illustrates the architecture of a conventional DRAM 100, which typically includes a matrixed arrangement of multiple memory cell arrays 105, each of which is understood to contain a matrixed arrangement of memory cells. The interstitial separations between the memory cell arrays 105 carry support circuits for addressing the memory cells in the memory cell arrays 105, such as for performing reading and writing operations. The interstitial separations include longitudinal streets 110 and latitudinal streets 115.
Longitudinal streets 110 typically include column decoder and sense amplifier circuits, which together are adjacent to or interposed between ones of memory cell arrays 105. The column decoder and sense amplifier circuits are used for reading data from and writing data to selected digit lines, which are in the memory cell arrays 105 and are coupled to memory cells therein. Latitudinal streets 115 typically include row decoders that are adjacent to or interposed between ones of memory cell arrays 105. The row decoder circuits are used for selectively activating word lines in a memory cell array 105 for accessing memory cells therein.
The column decoder and sense amplifier circuits in the longitudinal streets 110 and the row decoder circuits in the latitudinal streets 115 are sometimes referred to collectively as "pitch cell" circuits, because such circuits are laid out on the same pitch (spacing between adjacent ones) of the digit lines and word lines to which they are respectively coupled. The interstitial separations between memory cell arrays 105 occupy a considerable portion of the integrated circuit DRAM. In order to improve storage density, for reducing the component size of integrated circuit DRAM 100 or for increasing the data storage capability of integrated circuit DRAM 100, the magnitude of the interstitial separations between memory cell arrays 105 should be decreased, such as by electrical circuit design or physical layout design techniques. For example, it is known in the art to provide an output driver in a row decoder that is interposed between two memory cell arrays 105, where an output node of the output driver provides an output signal to a word line in each of the memory cell arrays 105 between which the row decoder is interposed. This reduces the size of the row decoder and the magnitude of the interstitial separations between memory cell arrays.
However, even if such design techniques are successful, there is a need in the art to provide, in a spatially efficient manner, control signals (e.g., addressing signals) to the row decoders in the latitudinal streets 115 and to the column decoders in the longitudinal streets 110. Thus, in order to fully realize the gains in storage density arising from reducing the magnitude of the interstitial separations between memory cell arrays 105, there is a need in the art to accommodate such magnitude reductions when providing signals to the pitch cells carried within the interstitial separations.